The present invention relates generally to semiconductor memory devices, and in particular, the present invention relates to a folded bit line memory cell structure including buried bit and word lines for a dynamic random access memory device.
The memory cells of dynamic random access memories (DRAMs) are comprised of two main components, a field-effect transistor (FET) and a capacitor which functions as a storage element The need to increase the storage capability of semiconductor memory devices has led to the development of very large scale integrated (VLSI) cells which provides a substantial increase in component density.
However, the extension of dynamic random access memories beyond the megabit range has placed large demands on the storage capacitance in single transistor memory cells. The problem is compounded by the trend for reduction in power supply voltages which results in stored charge reduction and leads to degradation of immunity to alpha particle induced soft errors, both of which require that the storage capacitance be even larger. As the cell size for dynamic random access memory (DRAM) cells is reduced to that necessary for Gigabit density and greater, there are three major impediments to cell size reduction which can be overcome only by significant innovation in the cell structure.
Cell structures used through the 256 Megabit generation have been fundamentally limited to a size of at least 8 F2, where F is a minimum lithographic feature size. This size limitation is imposed by the wiring requirements of passing both an active and passing word lines through the cell to achieve the low noise benefits of folded bit line architecture. This limitation can be removed by either relinquishing the folded bit line architecture or by devising a sub lithographic wiring technique. A further limitation is imposed by the area required to form the source region, the drain region and the channel region of the FET array device on a planar surface. Another limitation is imposed by the area that is required for fabricating the storage capacitor which, in a stacked capacitor technology, must compete with the bit line and word line wiring for space above the silicon surface.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a memory cell structure for a semiconductor memory device, such as dynamic random access memory device, which employs a folded bit line architecture and in which the surface area of the memory cells is minimized, providing a memory cell structure that is less than 8 F2 in size, resulting in increased density for the memory device.
The present invention provides a memory array cell structure for a semiconductor memory device. The memory array includes buried bit and word lines, and access transistors are formed as vertical structures on the bit lines. Isolation trenches extend orthogonally to the bit lines between the access transistors of adjacent memory cells. First and second word lines, which are located in each of the isolation trenches, are adapted to gate alternate ones of the access transistors located adjacent to the trench, allowing both an active and a passing word line to be contained within each memory cell, thereby providing a folded bit line architecture for the memory array. The width of the access transistors is determined by the width F of the bit lines, where F is a minimum feature size. The word line wiring is achieved on a 0.5F pitch by using sidewall spacer defined conductors that are oriented vertically widthwise within the trench. Thus, each memory cell of the memory array has a surface area that is approximately 4 F2 while maintaining a folded bit line architecture. The memory cell structure provided by the invention results in a high density semiconductor memory array having an improved topography and which achieves the low noise benefits of a folded bit line architecture.
Further in accordance with the invention, there is provided a method for producing a memory array including a plurality of memory cells on a semiconductor substrate. The method includes the steps of providing a semiconductor substrate and forming a plurality of layers of semiconducting material on a surface of the substrate, including a first layer of a material of a first conductivity type formed on the substrate, a second layer of a material of a second conductivity type formed on the first layer, and a third layer of a material of the first conductivity type formed on the second layer. Then, a plurality of first trenches are formed in the layers of semiconducting material to form a plurality of bars having the first, second and third layers of semiconducting material, with the first layer of semiconducting material of each of the bars functioning as a bit line for the memory array. A plurality of second trenches are formed in the stack of layers of semiconducting material in a direction that is orthogonal to the direction of the bit lines to define a plurality of in-line access transistors on each of the bit lines, with each of the access transistors having a vertical channel region, defined by the second layer of material, exposed in a sidewall of one of the second trenches. A gate oxide is formed on a sidewall of the trench, overlying the channel regions of each of the access transistors. Then, first and second word lines are formed in each of the second trenches, with the first word line extending in the proximity of the channel regions of the access transistors on first alternate ones of the bit lines; and with the second word line extending in the proximity of the channel regions of the access transistors on second alternate ones of the bit lines. Then, the second trenches are filled with a dielectric material to bury the first and second word lines in the dielectric material in the second trenches. The method can be carried out using either bulk silicon or silicon on insulator processing techniques.